PCIE Notes

PCI Express connector pinout (×1, ×4, ×8 and ×16 variants)

Pin	Side B	Side A	Description		Pin	Side B	Side A	Description
1	+12 V	PRSNT1#	Must connect to farthest PRSNT2# pin		50	HSOp(8)	Reserved	Lane 8 transmit data, + and −
2	+12 V	+12 V	Main power pins		51	HSOn(8)	Ground
3	+12 V	+12 V			52	Ground	HSIp(8)	Lane 8 receive data, + and −
4	Ground	Ground			53	Ground	HSIn(8)
5	SMCLK	TCK	SMBus and JTAG port pins		54	HSOp(9)	Ground	Lane 9 transmit data, + and −
6	SMDAT	TDI			55	HSOn(9)	Ground
7	Ground	TDO			56	Ground	HSIp(9)	Lane 9 receive data, + and −
8	+3.3 V	TMS			57	Ground	HSIn(9)
9	TRST#	+3.3 V			58	HSOp(10)	Ground	Lane 10 transmit data, + and −
10	+3.3 V aux	+3.3 V	Standby power		59	HSOn(10)	Ground
11	WAKE#	PERST#	Link reactivation; fundamental reset [23]		60	Ground	HSIp(10)	Lane 10 receive data, + and −
Key notch					61	Ground	HSIn(10)
12	CLKREQ#[24]	Ground	Clock Request Signal		62	HSOp(11)	Ground	Lane 11 transmit data, + and −
13	Ground	REFCLK+	Reference clock differential pair		63	HSOn(11)	Ground
14	HSOp(0)	REFCLK−	Lane 0 transmit data, + and −		64	Ground	HSIp(11)	Lane 11 receive data, + and −
15	HSOn(0)	Ground			65	Ground	HSIn(11)
16	Ground	HSIp(0)	Lane 0 receive data, + and −		66	HSOp(12)	Ground	Lane 12 transmit data, + and −
17	PRSNT2#	HSIn(0)			67	HSOn(12)	Ground
18	Ground	Ground			68	Ground	HSIp(12)	Lane 12 receive data, + and −
PCI Express ×1 cards end at pin 18					69	Ground	HSIn(12)
19	HSOp(1)	Reserved	Lane 1 transmit data, + and −		70	HSOp(13)	Ground	Lane 13 transmit data, + and −
20	HSOn(1)	Ground			71	HSOn(13)	Ground
21	Ground	HSIp(1)	Lane 1 receive data, + and −		72	Ground	HSIp(13)	Lane 13 receive data, + and −
22	Ground	HSIn(1)			73	Ground	HSIn(13)
23	HSOp(2)	Ground	Lane 2 transmit data, + and −		74	HSOp(14)	Ground	Lane 14 transmit data, + and −
24	HSOn(2)	Ground			75	HSOn(14)	Ground
25	Ground	HSIp(2)	Lane 2 receive data, + and −		76	Ground	HSIp(14)	Lane 14 receive data, + and −
26	Ground	HSIn(2)			77	Ground	HSIn(14)
27	HSOp(3)	Ground	Lane 3 transmit data, + and −		78	HSOp(15)	Ground	Lane 15 transmit data, + and −
28	HSOn(3)	Ground			79	HSOn(15)	Ground
29	Ground	HSIp(3)	Lane 3 receive data, + and −		80	Ground	HSIp(15)	Lane 15 receive data, + and −
30	PWRBRK#[25]	HSIn(3)			81	PRSNT2#	HSIn(15)
31	PRSNT2#	Ground			82	Reserved	Ground
32	Ground	Reserved
PCI Express ×4 cards end at pin 32
33	HSOp(4)	Reserved	Lane 4 transmit data, + and −
34	HSOn(4)	Ground
35	Ground	HSIp(4)	Lane 4 receive data, + and −
36	Ground	HSIn(4)
37	HSOp(5)	Ground	Lane 5 transmit data, + and −
38	HSOn(5)	Ground
39	Ground	HSIp(5)	Lane 5 receive data, + and −
40	Ground	HSIn(5)
41	HSOp(6)	Ground	Lane 6 transmit data, + and −
42	HSOn(6)	Ground
43	Ground	HSIp(6)	Lane 6 receive data, + and −		Legend
44	Ground	HSIn(6)			Ground pin		Zero volt reference
45	HSOp(7)	Ground	Lane 7 transmit data, + and −		Power pin		Supplies power to the PCIe card
46	HSOn(7)	Ground			Card-to-host pin		Signal from the card to the motherboard
47	Ground	HSIp(7)	Lane 7 receive data, + and −		Host-to-card pin		Signal from the motherboard to the card
48	PRSNT2#	HSIn(7)			Open drain		May be pulled low or sensed by multiple cards
49	Ground	Ground			Sense pin		Tied together on card
PCI Express ×8 cards end at pin 49					Reserved		Not presently used, do not connect

Additional Notes

M.2 is a form factor where is can be

- M.2 for SATA (Older Serial ATA)

- M.2 for NVME (uses PCIE)